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UPSD3422 Datasheet(PDF) 291 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 291 Page - STMicroelectronics |
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291 / 293 page ![]() uPSD34xx Important notes 291/293 34.12 Incorrect Code Execution when Code Banks are Switched Description When a code bank is switched, the PFQ/BC contain values from the previously selected bank and are not automatically flushed and reloaded from the newly selected code bank. Impact On Application. Depending on the contents of the PFQ/BC when the code bank is switched, improper code execution may result. Workaround. The PFQ/BC must be flushed when the code bank is changed. Disabling and re-enabling the PFQ/BC will flush them. The following instructions are an example of how to flush the PFQ/BC: ANL BUSCON,#03Fh ;Disable PFQ/BC ORL BUSCON,#0C0h ;Enable PFQ/BC Bank switching is typically handled by tool vendors in a file called l51_bank.a51. The uPSD tools offered by Keil and Raisonance now include an updated version of l51_bank.a51 for the uPSD products that flushes the PFQ/BC. The most recent banking examples available from ST's website include the updated l51_bank.a51 files. 34.13 9th Received Data Bit Corrupted in UART Modes 2 and 3 Description. If the 9th transmit data bit is written by firmware into TB8 at the same time as a received 9th bit is being written by the hardware into RB8, RB8 is not correctly updated. This applies to both UART0 and UART1. Typically, the 9th data bit is used as a parity bit to check for data transmission errors on a byte by byte basis. Impact on Application. UART Modes 2 and 3 can't be used reliably in full-duplex mode. Workaround. Revision A and B - Some options include: 1. Only use Mode 1 (8 data bits) for full-duplex communication. 2. Use Mode 1 and a packet based communication protocol with a checksum or CRC to detect data transmission errors. 3. Use UART0 in mode 2 or 3 for transmitting data and UART1 in mode 2 or 3 for receiving data. 4. Use some form of handshaking to ensure that data is never transmitted and received simultaneously on a single UART configured in mode 2 or 3. |
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