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TMP93CS32F Datasheet(PDF) 171 Page - Toshiba Semiconductor |
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TMP93CS32F Datasheet(HTML) 171 Page - Toshiba Semiconductor |
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171 / 180 page ![]() TMP93CS32 2004-02-10 93CS32-169 MSB LSB 9 8 7 6 5 4 3 2 1 0 Converted data of channel x ADREGxH ADREGxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 This is 1 when this is read. *1: Data to be stored in AD Conversion Result Reg Low are the lower 2 bits of the conversion result. The contents of the 5 to 1 bits of this register are always read as “1”. Bit0 conversion result stored flag bit <ADRxRF> <ADRxRF> is set to “1” when the AD conversion result is stored. Reading either the ADREGxH or the ADREGxL registers clears <ADRxRF> to “0”. (9) Watchdog timer Symbol Name Address 7 6 5 4 3 2 1 0 WDTE WDTP1 WDTP0 WARM HALTM1 HALTM0 RESCR DRVE R/W 1 0 0 0 0 0 0 0 WDMOD Watchdog timer mode control register 5CH 1: WDT enable 00: 2 15/fSYS 01: 2 17/fSYS 10: 2 19/fSYS 11: 2 21/fSYS Warm-up time 0: 2 14/Inputted frequency 1: 2 16/Inputted frequency HALT mode 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 1: Connect internally WDT out to reset pin 1: Drive the pin in STOP mode − W − WDCR Watchdog timer control register 5DH B1H: WDT disable code 4EH: WDT clear code |
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