UPSD3422EB40U6 datasheet(226/293 Pages) STMICROELECTRONICS

226 / 293 page

PSD module

uPSD34xx

226/293

following sections. Some operating modes can be defined using PSDsoft Express, and

some by the 8032 writing to the csiop registers at run-time, and some require both. For

example, PLD I/O, Latched Address Out, and Peripheral I/O modes must be defined in

PSDsoft Express and programmed into the device using JTAG, but an additional step must

happen at run-time to activate Latched Address Out mode and Peripheral I/O mode, but not

needed for PLD I/O. In another example, MCU I/O mode is controlled completely by the

8032 at run-time and only a simple pin name declaration is needed in PSDsoft Express for

documentation.

Table 116 on page 223 summarizes what actions are needed in PSDsoft Express and what

actions are required by the 8032 at run-time to achieve the various port functions.

Figure 80.

Detail of a single I/O port (typical of ports A, B, C)

Table 120.

Port operating modes

Port Operating Mode

Port A (80-pin

only)

Port B

Port C

Port D

Find it

MCU I/O

Yes

MCU I/O mode on

page 228

PLD I/O

OMC MCELLAB Outputs

OMC MCELLBC Outputs

External Chip-Select

Outputs

PLD Inputs

Yes

Yes(1)

Yes

PLD I/O mode on

page 230

I/O PORT

LOGIC

DIRECTION

DRIVE SELECT

CONTROL

DATA OUT (MCUI/O)

ENABLE OUT

DATA IN (MCUI/O)

D BIT, PERIPH I/O MODE, Port A

PT OUTPUT ENABLE (.OE)

LATCHED ADDR BIT, PORT A or B

MUX

8032

DATA

BIT

OUTPUT

DRIVER

TYPICAL

PORT A, B, C

PSD MODULE RESET

ONE of 6

CSIOP

REGISTERS

OUTPUT

SELECT

PERIPHERAL I/O

MODE SETS

DIRECTION

(PORT A ONLY)

FROM OMC OUTPUT

TO IMC

FROM PLD INPUT BUS

FROM AND-OR ARRAY

FROM OMC

ALLOCATOR

CLR

DIRECTION

DRIVE

CONTROL

(MCUI/O)

DATA OUT

RESET

PSDsoft

PSELx

PERIPH I/O

DATA BIT

CSIOP

REGIS-

TERS

DRIVE TYPE

8032

DATA

BITS

INPUT

BUFFER

OUTPUT ENABLE

RD PIO EN

8032

8032 RD

AI07873A

UPSD3422EB40U6 Datasheet(PDF) 226 Page - STMicroelectronics

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