PIC24FJ256GA705-ISLASHM4. datasheet(242/412 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118B-page 242

 2016 Microchip Technology Inc.

PMCON1: EPMP CONTROL REGISTER 1

R/W-0

U-0

R/W-0

U-0

R/W-0

PMPEN

—

PSIDL

ADRMUX1

ADRMUX0

—MODE1

MODE0

bit 15

bit 8

R/W-0

U-0

R/W-0

CSF1

CSF0

ALP

ALMODE

—

BUSKEEP

IRQM1

IRQM0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

PMPEN:

Parallel Master Port Enable bit

= EPMP is enabled

= EPMP is disabled

bit 14

Unimplemented:

Read as ‘0’

bit 13

PSIDL:

Parallel Master Port Stop in Idle Mode bit

= Discontinues module operation when device enters Idle mode

= Continues module operation in Idle mode

bit 12-11

ADRMUX<1:0>:

Address/Data Multiplexing Selection bits

= Lower address bits are multiplexed with data bits using 3 address phases

= Lower address bits are multiplexed with data bits using 2 address phases

= Lower address bits are multiplexed with data bits using 1 address phase

= Address and data appear on separate pins

bit 10

Unimplemented:

Read as ‘0’

bit 9-8

MODE<1:0>:

Parallel Port Mode Select bits

= Master mode

= Enhanced PSP; pins used are PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>

= Buffered PSP; pins used are PMRD, PMWR, PMCS and PMD<7:0>

= Legacy Parallel Slave Port; pins used are PMRD, PMWR, PMCS and PMD<7:0>

bit 7-6

CSF<1:0>:

Chip Select Function bits

= Reserved

= PMA14 is used for Chip Select 1

= Reserved

= PMCS2 is used for Chip Select 2, PMCS1 is used for Chip Select 1

bit 5

ALP:

Address Latch Polarity bit

= Active-high (PMALL, PMALH and PMALU)

= Active-low (PMALL, PMALH and PMALU)

bit 4

ALMODE:

Address Latch Strobe Mode bit

= Enables “smart” address strobes (each address phase is only present if the current access would

cause a different address in the latch than the previous address)

= Disables “smart” address strobes

bit 3

Unimplemented:

Read as ‘0’

bit 2

BUSKEEP:

Bus Keeper bit

= Data bus keeps its last value when not actively being driven

= Data bus is in a high-impedance state when not actively being driven

bit 1-0

IRQM<1:0>:

Interrupt Request Mode bits

= Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),

or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)

= Reserved

= Interrupt is generated at the end of a read/write cycle

= No interrupt is generated

PIC24FJ256GA705-I/M4. Datasheet(PDF) 242 Page - Microchip Technology

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