PIC24FJ256GA705-ISLASHM4. datasheet(102/412 Pages) MICROCHIP

102 / 412 page

PIC24FJ256GA705 FAMILY

DS30010118B-page 102

 2016 Microchip Technology Inc.

CLKDIV: CLOCK DIVIDER REGISTER

R/W-0

R/W-1

R/W-0

ROI

DOZE2

DOZE1

DOZE0

DOZEN(1)

RCDIV2

RCDIV1

RCDIV0

bit 15

bit 8

R/W-0

U-0

CPDIV1

CPDIV0

PLLEN

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ROI:

Recover on Interrupt bit

= Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1

= Interrupts have no effect on the DOZEN bit

bit 14-12

DOZE<2:0>:

CPU Peripheral Clock Ratio Select bits

111

= 1:128

110

= 1:64

101

= 1:32

100

= 1:16

011

= 1:8 (default)

010

= 1:4

001

= 1:2

000

= 1:1

bit 11

DOZEN:

Doze Enable bit(1)

= DOZE<2:0> bits specify the CPU peripheral clock ratio

= CPU peripheral clock ratio is set to 1:1

bit 10-8

RCDIV<2:0>:

System Frequency Divider Clock Source Select bits

111

= Reserved; do not use

110

= Reserved

101

= Low-Power RC Oscillator (LPRC)

100

= Secondary Oscillator (SOSC)

011

= Primary Oscillator (XT, HS, EC) with PLL module (XTPLL, HSPLL, ECPLL)

010

= Primary Oscillator (XT, HS, EC)

001

= Fast RC Oscillator (FRC) with PLL module (FRCPLL)

000

= Fast RC Oscillator (FRC)

bit 7-6

CPDIV<1:0>:

System Clock Select bits (postscaler select from PLL, 32 MHz clock branch)

= 4 MHz (divide-by-8)

= 8 MHz (divide-by-4)

= 16 MHz (divide-by-2)

= 32 MHz (divide-by-1)

bit 5

PLLEN:

PLL Enable bit

= PLL is always active

= PLL is only active when a PLL Oscillator mode is selected (OSCCON<14:12> = 011 or 001)

bit 4-0

Unimplemented:

Read as ‘0’

Note 1:

This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

PIC24FJ256GA705-I/M4. Datasheet(PDF) 102 Page - Microchip Technology

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