L9679P datasheet(175/279 Pages) STMICROELECTRONICS

175 / 279 page

DS11627 Rev 7

175/279

L9679P

Remote sensor interface

278

Figure 42. PSI5 slot timing control

The remote sensor interface is also able to detect faults occurring on the sensor interface.

The Remote Sensor Data Register (RSDRx) will report multiple fault flags.

When the number of bits decoded is incorrect (either too many or too few), a bit error is

indicated. When any bit error is detected (bit time, too many bits, too few bits), the decoder

will revert to the minimum bit time of the selected range and the message is discarded.

Error bit INVALID is an OR-ed combination of the following errors:



Start bit error outside of selected operating range



Data length error or stop bit error



Parity Error of received Remote sensor Message



Bit time error (a data bit edge is not received inside the expected time window)

All fault bits related to channel error are loaded in the 3 time slot register and the fault has

the priority, so the fault overwrite valid data.

9.1.2

Sensor data integrity: LCID and CRC

Each RSDRx data register contains a Logical Channel ID which is a 4/2-bit field for remote

sensors used to link the received data to the corresponding logical channel number. Each

RSDRx register contains also a CRC bit field computed on the data packet for data integrity

check. To satisfy functional safety requirements LCID, DATA and CRC bit fields propagate

through the same data path as a single item to the SPI output.

The polynomial calculation implemented for PSI5 data is described as in PSI5 specification

g(x)=1+x+x^3 with initialization value equal to ‘111’.

Below are the equations to calculate the CRC in combinatorial way.

CRC[2] = CRCext[0]+D[0]+D[1]+D[3]+D[6]+D[7]+D[8]+D[10]+D[13]+D[14]+D[15]

328.9

T_ES_1

T_LS_1

T_EE_1

T_LE_1T_ES_2 T_LS_2

T_EE_2

T_LE_2 T_ES_3 T_LS_3

T_EE_3

T_LE_3

T_s1_end_open(min)

T_s1_end_open(max)

T_s1_end_closure(min)

T_s1_end_closure(max)

PSI5 frames

From Satellite

Frame end

Detect windows

Slot 1

Slot 2

Slot 3

Receiver

Response

Error Slot 1

Valid

Slot 1

Error Slot 1

Valid

Slot 2

Error

Slot 2

Valid

Slot 3

Error Slot 3

SYNC PULSE ENABLE

SATSYNC PIN

Stop bit not

included

T_s2_end_open(min)

T_s2_end_open(max)

T_s3_end_open(min)

T_s3_end_open(max)

T_s2_end_closure(min)

T_s2_end_closure(max)

T_s3_end_closure(min)

T_s3_end_closure(max)

GAPGPS03314

L9679P Datasheet(PDF) 175 Page - STMicroelectronics

L9679P Datasheet(HTML) 175 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL