L9679P datasheet(183/279 Pages) STMICROELECTRONICS

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DS11627 Rev 7

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L9679P

Watchdog timers

278

10.1.2

Watchdog timer operation

While in the WD1_INITIAL state, watchdog service must begin or a SPI command with

WD1_TO_DIS=1 must be received within the first 500 ms. If the WD1 Timeout Disable bit is

set, the device can stay in the WD1_INITIAL state indefinitely without watchdog service.

To refresh WD1, the logic must receive a Watchdog Timer Register (WD1T) SPI command

containing the expected key value within the WD1 time window (WDTMIN+WDTDELTA). If

it is received too early, too late the WD1_ERROR signal will be asserted. The WD1_ERROR

will not be asserted in case a SPI command containing the Watchdog Timer Register

(WD1T) with an incorrect key value is received at any time relative to the window. This

allows the system software to repeatedly transmit the key value until it needs to change to

the correct key value. Upon reception of the correct key within the window, the logic will

reset the watchdog timer to create a new window.

The timer is cleared upon writing code 'A' and code 'B' (either in 'A' - 'B' or 'B' - 'A'

sequences) to the WD1CTL [1:0] bits, in the WD1T register. The watchdog timer value can

be read via the WD1T register.

Figure 45. Watchdog timer refresh diagram

GAPGPS01659

WD1INIT

WD1A1

WD1B1

WD1B2

WD1A2

WD1_ERROR

SPI_WD1_B

SPI_WD1_B /

TMR1=0

Strobe WD1 refresh OK

SPI_WD1_A /

TMR1=0

Strobe WD1 refresh OK

PI_WD1_A

SSM_RESET

TMR1>MIN &

SPI_WD1_A /

TMR1=0

Strobe WD1 refresh OK

TMR1>MIN &

SPI_WD1_B /

TMR1=0

Strobe WD1 refresh OK

TMR1>MAX OR

[TMR1<MIN & SPI_WD1_B]

TMR1>MAX OR

[TMR1<MIN & SPI_WD1_A]

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