L9679P datasheet(208/279 Pages) STMICROELECTRONICS

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General purpose output (GPO) drivers

L9679P

208/279

DS11627 Rev 7

General purpose output (GPO) drivers

The L9679P contains three General Purpose Output (GPO) drivers configurable either as

high-side or low-side modes. The drivers can be independently controlled in ON-OFF mode

or in PWM mode setting the desired duty cycle value through the GPO Control Register

(GPOCTRLx).

For low side driver configuration, the GPODx pin is the drain connection of an internal

MOSFET and is the current sink for the output driver. The GPOSx pin is the source

connection of the internal MOSFET and is externally connected to ground. For high side

driver configuration, the GPODx pin will be connected to battery and GPOSx pin will be

connected to load's high side.

Figure 65. GPO driver and diagnostic block diagram

The drivers are configured in one of the two modes through the GPO Configuration Register

(GPOCR) register. This hardware configuration is only allowed during the Init and Diag

states.

When configured as high-side, the drivers need ER Boost voltage to be above the

VERBST_OK threshold to be enabled.

The default state of all drivers is off. The drivers can be independently activated via SPI

control bits on GPO Control Register (GPOCTRLx). In addition, a set point on the

GPOCTRLx will control the output drivers in PWM with a 125Hz frequency. If PWM control is

desired, user should set the needed set point in the GPOxPWM bits of the GPOCTRLx

while activating the interface. When all bits are set to '0', the GPOx output will be disabled.

GAPGPS02302

)

GPOFLTSR(GPOxTEMP

ERBOOST_OK

GPOCR(GPOxLS)

SPI(RID=‘GPOFLTSR’)

SSM_RESET

GPOCTRLx[5:0]

GPOCR(GPOxLS)

SSM_RESET

SPI(WID=‘GPOCR’)

(8kHz / 125μs)

PWM_CLK

OUT

PWM CTL

CTL

VOUT_GPOx_OL

OFF

GPOFLTSR(GPOxDISABLE)

GPOSx

GPODx

GPOFLTSR(GPOxONOPN)

GPOFLTSR(GPOxOFFOPN)

GPOFLTSR(GPOxOC)

GPOFLTSR(GPOxSHORT)

IDS > IOC_GPO

IDS < IOL_GPO

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