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SPSB100 Datasheet(PDF) 117 Page - STMicroelectronics |
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SPSB100 Datasheet(HTML) 117 Page - STMicroelectronics |
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117 / 213 page  Bit Mode 0x30 DSR16 MSB RES RES RES RES R RES RES IGN_9 IGN_8 LSB IGN_3 IGN_2 IGN_1 IGN_0 0x31 DSR17 MSB RES RES RES RES R RES RES FBB_9 FBB_8 LSB FBB_3 FBB_2 FBB_1 FBB_0 0x32 DSR18 MSB RES RES RES BUCK2_FBLOSS R WD_TIME_STATUS_1 WD_TIME_STATUS_0 VBUCK3_ENA_STATUS VBUCK2_ENA_STATUS LSB BOOST_ENA_STATUS FCCU_ENA_STATUS RES RES Table 58. Status register overview (bit 27...24) lower nibbles Bit Mode 27 26 25 24 Global status FE1 DE GW FS R Status register Bit Mode Addr. 19 18 17 16 11 10 9 8 CRC 3 CRC 2 CRC 1 CRC 0 0x21 DSR1 MSB BUCK3_OV BUCK3_UV BUCK3_PG_TIMEOUT BUCK2_OC R BUCK1_OV BUCK1_UV BUCK1_PG_TIMEOUT LDO2_PG_TIMEOUT LSB CRC 3 CRC 2 CRC 1 CRC 0 0x22 DSR2 MSB BYPASS_VDSMON_ERROR BOOST_VDSMON_ERROR FBB_OV FBB_UV R NRST_ECHO_ERROR VIO_UV TSD_CL4 TSD_CL3 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x23 DSR3 MSB BUCK1_INT_FAIL LBIST_ERROR_1 LBIST_ERROR_0 ABIST_ERROR R INT_REG_UV INT_REG_OV NVM_COMP_ERROR NVM_CRC_ERROR LSB CRC 3 CRC 2 CRC 1 CRC 0 0x24 DSR4 MSB SPI_CRC_ERR SPI_SDI_STUCK_HIGH SPI_SDI_STUCK_LOW SPI_UNDEF_ADD R VS_UV_EW RES TW_CL4 TW_CL3 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x25 DSR5 MSB BYPASS_STATUS BUCK3_PG_OK BUCK2_PG_OK BUCK1_PG_OK R DEV_STATE_1 DEV_STATE_0 DEEP-SLEEP_FROM_DO_POWER_DOWN_1 DEEP-SLEEP_FROM_DO_POWER_DOWN_0 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x26 DSR6 MSB RES RES RES RES R IGN_WAKE WU_WAKE RES TIMER_WAKE LSB CRC 3 CRC 2 CRC 1 CRC 0 0x27 DSR7 MSB LDO2_PG_OK FCCU_ENA_ECHO WD_ENA_ECHO WD_TIMER_STATE_1 R WDFAIL_CNT_0 TSD_CNT_FAIL_1 TSD_CNT_FAIL_0 POWUP_RETRY_CNT_1 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x28 DSR8 MSB FCCU_LAST_STABLE_9 FCCU_LAST_STABLE_8 FCCU_LAST_STABLE_7 FCCU_LAST_STABLE_6 R FCCU_LAST_STABLE_1 FCCU_LAST_STABLE_0 FORCED_SLEEP_REGFAIL REG_FAIL_CNT_1 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x29 DSR9 MSB RES RES RES RES R TEMP_CL0_7 TEMP_CL0_6 TEMP_CL0_5 TEMP_CL0_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x2A DSR10 MSB RES RES RES RES R TEMP_CL1_7 TEMP_CL1_6 TEMP_CL1_5 TEMP_CL1_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x2B DSR11 MSB RES RES RES RES R TEMP_CL2_7 TEMP_CL2_6 TEMP_CL2_5 TEMP_CL2_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 0x2C DSR12 MSB RES RES RES RES R TEMP_CL3_7 TEMP_CL3_6 TEMP_CL3_5 TEMP_CL3_4 LSB CRC 3 CRC 2 CRC 1 CRC 0 SPSB100 SPI registers DS14640 - Rev 2 page 117/213 |
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