DP83867CS datasheet(118/129 Pages) TI2

118 / 129 page

• Remove the duplicate timing diagram.............................................................................................................. 13

• Edit Wake on Lan section.................................................................................................................................20

• Edit Magic Packet Structure............................................................................................................................. 20

• Change Magic Packet Example....................................................................................................................... 21

• Edit Wake-on-LAN Configuration and Status................................................................................................... 21

• Added section Section 7.3.2.1 .........................................................................................................................22

• Edit Extended Address Space Access............................................................................................................. 29

• Edit Write (No Post Increment) Operation........................................................................................................ 29

• Edit Read (No Post Increment) Operation........................................................................................................30

• Edit Write (Post Increment) Operation..............................................................................................................30

• Edit Read (Post Increment) Operation............................................................................................................. 30

• Clean up the language..................................................................................................................................... 31

• Clarify register 0x0004 half duplex advertisement bit ......................................................................................45

• Updated Auto-Negotiation Advertisement Register (ANAR) register............................................................... 49

• Edit default value for bit [1:0]............................................................................................................................76

• Added Section 7.6.37 register.......................................................................................................................... 79

• Add register 0x00A0 content............................................................................................................................ 83

• Add register 0x00A1 content............................................................................................................................ 84

• Add register 0x00A2 content............................................................................................................................ 84

• Add register 0x00A3 content............................................................................................................................ 84

• Added Section 7.6.54 register.......................................................................................................................... 86

• Add TDR Peak Sign info.................................................................................................................................102

• Updated the Cable Line Driver section...........................................................................................................105

• Add a note on power supply recommendation sesssion ............................................................................... 110

Changes from Revision C (October 2019) to Revision D (November 2022)

Page

• Updated Start of Frame Detect for IEEE 1588 time stamp.................................................................................1

• Updated Electrical Characteristics......................................................................................................................9

• Added Phy has internal 100 Ohm differential termination in Section 7.4.1.1 .................................................. 24

• Added following wording to the end of first paragraph in Section 7.4.3.9 "DP83867 devices manufactured

after August, 2022, have an increased random seed value that now includes 255 different seed values to

expedite Auto-MDIX resolution with a link partner."..........................................................................................33

• Changed Bit 11:10 SPEED_OPT_ATTEMPT_CNT to RW description in ....................................................... 65

• Changed bits 15:9, so that bit 12 can be '1'. Bit 7 description updated Section 7.6.31 ...................................76

• Added Register 0x008A....................................................................................................................................82

• Added Register 0x00B3....................................................................................................................................84

• Added Register 0x00C0................................................................................................................................... 85

• Added Register 0x0100.................................................................................................................................... 86

Changes from Revision B (March 2017) to Revision C (October 2019)

Page

• Added "Time Sensitive Network (TSN) Compliant" to Section 1 ....................................................................... 1

• Changed "Fast Link up / Link Drop Modes" to "Fast Link Drop Mode" in Section 1 ..........................................1

• Added "Field Bus Support" to Section 2 ............................................................................................................1

• Deleted "NOTE: Internal pullup and pulldown resistors on the IO pins are disabled when the device enters

functional mode after power up." from Pin Functions.........................................................................................4

• Added XI pin voltage ratings to Section 6.1 ...................................................................................................... 8

• Added XI Input Voltage section to Section 6.5 .................................................................................................. 9

• Added SGMII Latency nominal values to Section 6.9 ..................................................................................... 12

• Changed links to RGMII timing diagrams in Section 6.10 ............................................................................... 12

• Changed TholdR parameter description in Section 6.10 ................................................................................... 12

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

www.ti.com

118

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