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STM32F301C6 Datasheet(PDF) 110 Page - STMicroelectronics |
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STM32F301C6 Datasheet(HTML) 110 Page - STMicroelectronics |
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110 / 141 page ![]() Electrical characteristics STM32F301x6 STM32F301x8 110/141 DS9895 Rev 8 Figure 34. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.20 Comparator characteristics Update rate(3) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) CLOAD ≤50 pF, RLOAD ≥ 5 kΩ -- 1 MS/s tWAKEUP(3) Wakeup time from off state (Setting the ENx bit in the DAC Control register) CLOAD ≤50 pF, RLOAD ≥ 5 kΩ - 6.5 10 µs PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement CLOAD = 50 pF, No RLOAD ≥ 5 kΩ, - –67 –40 dB 1. Guaranteed by design. 2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is involved. 3. Guaranteed by characterization results. Table 68. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Buffered/Non-buffered DAC DAC_OUTx Buffer 12-bit digital to analog converter (1) RL CL MS39009V1 Table 69. Comparator characteristics(1)(2) Symbol Parameter Conditions Min. Typ. Max. Unit VDDA Analog supply voltage - 2 - 3.6 V VIN Comparator input voltage range -0 - VDDA V VBG Scaler input voltage - - VREFINIT - VSC Scaler offset voltage - - ±5 ±10 mV |
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