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MPF0900AMBA2ES Datasheet(PDF) 200 Page - NXP Semiconductors

Part # MPF0900AMBA2ES
Description  Nine-channel power management IC with advanced system safety monitoring
PDF  205 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF0900AMBA2ES Datasheet(HTML) 200 Page - NXP Semiconductors

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NXP Semiconductors
PF09
Nine-channel power management IC with advanced system safety monitoring
Tables
Tab. 1.
Ordering information ..........................................6
Tab. 2.
Ordering options ................................................6
Tab. 3.
Device versioning strategy ................................ 7
Tab. 4.
QFN56 Pin description ....................................11
Tab. 5.
PF09 voltage regulator summary. ................... 14
Tab. 6.
DEVICE_ID bit field .........................................15
Tab. 7.
FS_ID bit field ................................................. 15
Tab. 8.
DEVICE_FAM bit field .....................................15
Tab. 9.
PROG_IDH bit field .........................................15
Tab. 10. PROG_IDL bit field ......................................... 16
Tab. 11. OTP_VIN_SEL bit ........................................... 17
Tab. 12. VIN_POR thresholds .......................................19
Tab. 13. OTP_LP_STBY bit .......................................... 22
Tab. 14. STANDBY operation summary ........................22
Tab. 15. OTP_PWRON_DFS bit ................................... 24
Tab. 16. OTP_RETRY_DFS bit .....................................24
Tab. 17. Auto-retry timer summary ................................25
Tab. 18. Autoretry dynamic characteristics ................... 25
Tab. 19. Auto-retry time base ........................................26
Tab. 20. VDDOTP pin electrical characteristics .............26
Tab. 21. Sys_Diag (register 0x82 ) ................................27
Tab. 22. UVDET electrical characteristics ..................... 28
Tab. 23. VIN_OV_EN bit ............................................... 28
Tab. 24. VIN_OV_SDWN bit ......................................... 28
Tab. 25. VIN_OV_DBNC bit field .................................. 29
Tab. 26. VIN_OV electrical characteristics .................... 29
Tab. 27. IC startup dynamic characteristics .................. 33
Tab. 28. Default sequencer time base .......................... 34
Tab. 29. List of channels with selectable power-up
sequencing ...................................................... 35
Tab. 30. Channel sequence .......................................... 35
Tab. 31. Dynamic power down sequence example ....... 37
Tab. 32. Dynamic sequence settling time ......................38
Tab. 33. VAON reaction on XFAILB .............................. 39
Tab. 34. VAON always-on reset reaction ...................... 40
Tab. 35. Soft reset impact .............................................40
Tab. 36. WD duration on soft reset ............................... 41
Tab. 37. Effect of soft reset on GPO .............................41
Tab. 38. Effect of soft reset on system regulators ......... 41
Tab. 39. Effect of soft reset on external VMON input .... 41
Tab. 40. RSTB pulse on soft reset ................................42
Tab. 41. EWARN delay time ......................................... 44
Tab. 42. Delay after power-down sequence ..................45
Tab. 43. Regulation reaction on OV condition ...............49
Tab. 44. Regulation reaction on UV condition ............... 49
Tab. 45. Bits used to disable regulator during UV or
OV ................................................................... 49
Tab. 46. Output re-enable ............................................. 49
Tab. 47. ILIM protection bypass bit ............................... 50
Tab. 48. OV protection bypass bit .................................50
Tab. 49. UV protection bypass bit ................................. 50
Tab. 50. Bits to enable/disable regulators at UV/OV ..... 50
Tab. 51. Fault timer ....................................................... 51
Tab. 52. VAON fault timer duration ............................... 53
Tab. 53. VAON always-on fault management
strategy ............................................................54
Tab. 54. VAON System regulator fault management .....55
Tab. 55. OTP_PWRUP_CHK bit ................................... 55
Tab. 56. System diagnostic flags .................................. 59
Tab. 57. Hard-fault Flags ...............................................59
Tab. 58. System interrupt flags ..................................... 60
Tab. 59. Interrupt latch, interrupt mask, and sense
bits ...................................................................60
Tab. 60. Interrupt register set ........................................61
Tab. 61. I/O pin sense bits ............................................61
Tab. 62. SYS_CMD[7:0] bit field ................................... 62
Tab. 63. Electrical characteristics ..................................63
Tab. 64. PWRON operation mode ................................ 68
Tab. 65. Time to reset ...................................................68
Tab. 66. PWRON pin debounce ....................................69
Tab. 67. STBY pin polarity ............................................ 69
Tab. 68. STANDBY request window ..............................70
Tab. 69. RSTB buffer type ............................................ 70
Tab. 70. RSTB short-detection timer .............................71
Tab. 71. State of RSTB pin ...........................................71
Tab. 72. Voltage reels PGOOD triggers ........................ 72
Tab. 73. PGOOD_S flag ................................................73
Tab. 74. FS0B Fault control bits ....................................74
Tab. 75. FCCU1 pin operation when FCCU block is
not available in the system. .............................74
Tab. 76. FCCU1 pin operation when FCCU block is
available in the system. ...................................75
Tab. 77. XRESET polarity ............................................. 75
Tab. 78. XRESET debounce timer ................................ 75
Tab. 79. XRST_MODE .................................................. 76
Tab. 80. XRST_STBY_EN bit ........................................76
Tab. 81. GPIO1 mode ................................................... 76
Tab. 82. GPIO1_S flag .................................................. 76
Tab. 83. GPIO1 state in RUN ....................................... 77
Tab. 84. GPIO1 state in STANDBY ...............................77
Tab. 85. LDO2 voltage selection ...................................77
Tab. 86. GPIO2 mode ................................................... 78
Tab. 87. GPIO2_S flag .................................................. 78
Tab. 88. GPIO2 state in RUN ....................................... 78
Tab. 89. GPIO2 state in STANDBY ...............................78
Tab. 90. LDO1EN mode ................................................79
Tab. 91. GPIO3 mode ................................................... 79
Tab. 92. GPIO3 state .................................................... 79
Tab. 93. GPIO3 state in RUN state ...............................80
Tab. 94. GPIO3 state in STANDBY state ...................... 80
Tab. 95. GPIO4 mode ................................................... 80
Tab. 96. GPIO4_S flag .................................................. 80
Tab. 97. GPIO4 state in RUN ....................................... 81
Tab. 98. GPIO4 state in STANDBY ...............................81
Tab. 99. XFAIL operation .............................................. 81
Tab. 100. I2C mode of operations ...................................84
Tab. 101. Setting up the I2C device address .................. 84
Tab. 102. Enabling the I2C CRC mechanism ..................85
Tab. 103. Enabling I2C secure write ............................... 86
Tab. 104. Bit groups that may require a secure write
protocol ............................................................86
Tab. 105. VANA overvoltage status ................................ 90
PF09
All information provided in this document is subject to legal disclaimers.
© 2026 NXP B.V. All rights reserved.
Product data sheet
Rev. 1.3 — 16 December 2025
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