MPF0900AMBA2ES datasheet(125/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

needed by the system during the system configuration stage to ensure no false OV conditions are detected

during safe system operation.

OV_DBNC[1:0]

OV debounce time

25 µs

50 µs

80 µs

125 µs

Table 163. OV debounce time configuration bits

The debounce time required for an UV condition to be detected can be programmed in the functional register

via the UV_DBNC[1:0] bits. The UV debounce time is global for all voltage monitors, and, by default, the

configuration, is reset to the lowest condition (0b00) at power-up. The MCU must configure the actual value

needed by the system during the system configuration stage to ensure no false UV conditions are detected

during safe system operation.

UV_DBNC[1:0]

UV debounce time

5 µs

15 µs

25 µs

40 µs

Table 164. UV debounce time configuration bits

13.3.1.1 VMON during SW1 load switch operation

When the SW1 is programmed in load switch mode, the PF09 is expected to have a 3.3 V input supply and the

output of the SW1LS is expected to follow the 3.3 V minus the DC voltage drop due to the current going through

the SW1LS pass FET.

The system designer must select the proper voltage monitoring level during the RUN and the Monitored

STANDBY states via the VSW1_RUN[7:0] and VSW1_STBY[7:0] bits respectively. Likewise, the system must

provide adequate OV/UV thresholds to account for the voltage drop due to DC losses in the pass FET.

OV/UV monitoring thresholds for the load switch operation are configured in the OTP registers via the

OTP_SW1_OVTH[2:0] and OTP_SW1_UVTH[2:0] bits.

13.3.1.2 VMON during LDOx load switch operation

When the LDOx is programmed in load switch mode, the LDO block is capable of receiving an input supply

between 1.8 V and 3.3 V, and the output of the LDOxLS is expected to follow the input voltage minus the DC

voltage drop due to the current going through the LDOxLS pass FET.

The system designer must select the proper voltage monitoring level during the RUN and the Monitored

STANDBY states via the VLDOx_RUN[4:0] and VLDOx_STBY[4:0] bits respectively. Likewise, the system must

provide adequate OV/UV thresholds to account for the voltage drop due to DC losses in the pass FET.

OV/UV monitoring thresholds for the load switch operation are configured in the OTP registers via the

OTP_LDOx_OVTH[2:0] and OTP_LDOx_UVTH[2:0] bits.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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