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STM32L4P5CE Datasheet(PDF) 275 Page - STMicroelectronics

Part # STM32L4P5CE
Description  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150 DMIPS, up to 1-MB Flash memory, 320-KB SRAM, LCD-TFT, ext. SMPS
PDF  311 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L4P5CE Datasheet(HTML) 275 Page - STMicroelectronics

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DS12903 Rev 2
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STM32L4P5xx
Electrical characteristics
277
6.3.33
SD/SDIO/MMC card host interfaces (SDMMC)
Unless otherwise specified, the parameters given in Table 122 for SDIO are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 21: General operating conditions with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 x VDD Refer to Section 6.3.14: I/O
port characteristics for more details on the input/output characteristics.
Table 122. Dynamics characteristics:
SD / eMMC characteristics at VDD = 2.7 V to 3.6 V (1)
1. Guaranteed by characterization results.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer
mode
-0
-
64
MHz
-
SDIO_CK/fPCLK2 frequency
ratio
--
-
8/3
-
tW(CKL)
Clock low time
fpp = 52 MHz
8.5
9.5
-
ns
tW(CKH)
Clock high time
fpp = 52 MHz
8.5
9.5
-
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode
2. For SD 1.8 V support, an external voltage converter is needed.
tISU
Input setup time HS
-
1.5
-
-
ns
tIHD
Input hold time HS
-
2.0
-
-
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode
tOV
Output valid time HS
-
-
5.5
7
ns
tOH
Output hold time HS
-
4
-
-
CMD, D inputs (referenced to CK) in SD default mode
tISUD
Input setup time SD
-
0.5
-
-
ns
tIHD
Input hold time SD
-
1.5
-
-
CMD, D outputs (referenced to CK) in SD default mode
tOVD
Output valid default time SD
-
-
1
2
ns
tOHD
Output hold default time SD
-
0
-
-



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