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STM32L4P5CEI3P Datasheet(PDF) 266 Page - STMicroelectronics

Part # STM32L4P5CEI3P
Description  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150 DMIPS, up to 1-MB Flash memory, 320-KB SRAM, LCD-TFT, ext. SMPS
PDF  311 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L4P5CEI3P Datasheet(HTML) 266 Page - STMicroelectronics

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Electrical characteristics
STM32L4P5xx
266/311
DS12903 Rev 2
Figure 60. OCTOSPI timing diagram - SDR mode
Figure 61. OCTOSPI timing diagram - DDR mode
tvr(OUT)
tvf(OUT)
Data output valid time
Voltage
Range V1
DHQC =0
-
5.75
7.75
ns
DHQC =1
Pres=1,2
...
-
Tpclk/4
+0.75
Tpclk/4
+1.5
Voltage
Range V2
DHQC =0
-
8
11
thr(OUT)
thf(OUT)
Data output hold time
Voltage
Range V1
DHQC =0
0.5
-
-
DHQC =1
Pres=1,2
...
Tpclk/4
-0.25
-
-
Voltage Range V2
DHQC=0
5-
-
1. Guaranteed by characterization results.
2. Maximum frequency values are given for an RWDS to DQ skew of maximum +/-1.0ns
3. Activating DHQC is mandatory to reach this frequency.
4. All clk/clk# pairs are in line with HyperMemory AC differential crossing voltage margins except pairs including PB10 and
PH7.
5. Data input setup time maximum does not take into account data level switching duration.
Table 116. OCTOSPI characteristics in DTR mode (with DQS)(1)/Octal and Hyperbus (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MSv36878V1
Data output
D0
D1
D2
Clock
Data input
D0
D1
D2
t(CK)
tw(CKH)
tw(CKL)
tr(CK)
tf(CK)
ts(IN)
th(IN)
tv(OUT)
th(OUT)
MSv36879V3
Data output
IO0
IO2
IO4
Clock
Data input
IO0
IO2
IO4
t(CLK)
tw(CLKH)
tw(CLKL)
tr(CLK)
tf(CLK)
tsf(IN) thf(IN)
tvf(OUT)
thr(OUT)
IO1
IO3
IO5
IO1
IO3
IO5
tvr(OUT)
thf(OUT)
tsr(IN) thr(IN)



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