ST7FOXF1 datasheet(113/226 Pages) STMICROELECTRONICS

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ST7FOXF1, ST7FOXK1, ST7FOXK2

On-chip peripherals

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In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite

timer stops counting and is no longer able to generate a Watchdog reset until the

microcontroller receives an external interrupt or a reset.

If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a

reset is generated, the Watchdog is disabled (reset state).

Recommendations

●

Make sure that an external event is available to wake up the microcontroller from Halt

mode.

●

Before executing the HALT instruction, refresh the WDGD bit, to avoid an unexpected

Watchdog reset immediately after waking up the microcontroller.

●

When using an external interrupt to wake up the microcontroller, reinitialize the

corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT

instruction. The main reason for this is that the I/O may be wrongly configured due to

external interference or by an unforeseen logical condition.

●

For the same reason, reinitialize the level sensitiveness of each external interrupt as a

precautionary measure.

Figure 54.

Watchdog timing diagram

10.3.4

Low power modes

tWDG

fWDG

INTERNAL

WATCHDOG

RESET

WDGD BIT

SOFTWARE SETS

WDGD BIT

HARDWARE CLEARS

WDGD BIT

WATCHDOG RESET

(2ms @ 8MHz fOSC)

Table 39.

Effect of low power modes on Lite timer 2

Mode

Description

Slow

No effect on Lite timer

(this peripheral is driven directly by fOSC/32)

Wait

No effect on Lite timer

Active Halt

No effect on Lite timer

Halt

Lite timer stops counting

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