R5F5651CDDFM datasheet(101/188 Pages) RENESAS

101 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 101 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4.2

Clock Timing

Figure 2.3

BCLK Pin and SDCLK Pin Output Timing

Table 2.15

BCLK Pin Output, SDCLK Pin Output Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

BCLK pin output cycle time

Package of 144 pins or more

tBcyc

16.6

—

Figure 2.3

100-pin package

33.2

—

BCLK pin output high pulse width

tCH

3.3

—

BCLK pin output low pulse width

tCL

3.3

—

BCLK pin output rising time

tCr

——

BCLK pin output falling time

tCf

——

SDCLK pin output cycle time

Package of 144 pins or more

tBcyc

16.6

—

SDCLK pin output high pulse width

tCH

3.3

—

SDCLK pin output low pulse width

tCL

3.3

—

SDCLK pin output rising time

tCr

——

SDCLK pin output falling time

tCf

——

tCf

tCH

tBcyc, tSDcyc

tCr

tCL

BCLK pin output, SDCLK pin output

Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF

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