R5F5671CDDFB datasheet(126/179 Pages) RENESAS

126 / 179 page

R01DS0373EJ0120 Rev.1.20

Page 126 of 179

Sep 30, 2024

RX671 Group

2. Electrical Characteristics

Note:

tPcyc refers to the period of PCLKA in SCI10 and SCI11, and of PCLKB in SCI0 to SCI9, and SCI12.

Figure 2.50

Simple SPI Clock Timing

Table 2.38

Simple SPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

Simple

SPI

SCK clock cycle output (master)

tSPcyc

4—

tPcyc

Figure 2.50

SCK clock cycle input (slave)

—

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

tSPCKr, tSPCKf

—20

Data input setup time

tSU

33.3

—

Figure 2.51 to

Figure 2.54

Data input hold time

33.3

—

SS input setup time

tLEAD

1—

tSPcyc

SS input hold time

tLAG

1—

tSPcyc

Data output delay time

tOD

—

33.3

Data output hold time

tOH

–10

—

Data rise/fall time

tDr, tDf

—

16.6

SS input rise/fall time

tSSLr, tSSLf

—

16.6

Slave access time

tSA

—5

tPcyc

Figure 2.53,

Figure 2.54

Slave output release time

tREL

—5

tPcyc

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

(n = 0 to 12)

SCKn output

(master)

SCKn input

(slave)

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