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ST10F280 Datasheet(PDF) 133 Page - STMicroelectronics |
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ST10F280 Datasheet(HTML) 133 Page - STMicroelectronics |
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133 / 186 page  ST10F280 133/186 Figure 68 : Internal (simplified) Reset Circuitry. RSTOUT EINIT Instruction Trigger Clr Clock Reset State Machine Internal Reset Signal Reset Sequence (512 CPU Clock Cycles) SRST instruction watchdog overflow RSTIN VCC BDRSTEN VCC RPD Weak pull-down (~200 µA) From/to Exit Powerdown Circuit Asynchronous Reset Clr Q Set Figure 69 : Minimum External Reset Circuitry ST10F280 External Hardware RSTOUT + RSTIN a) Manual Hardware Reset C1 b) For Automatic Power-up Reset and interruptible power-down mode VDD R0 RPD + C0 |
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