SABRE-LL-I datasheet(127/141 Pages) STMICROELECTRONICS

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SABRE-LL-I

Serial interface

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Serial interface

S.A.B.Re can communicate with an external microprocessor by using an integrated slave

SPI (Serial Protocol Interface). Through this interface almost all S.A.B.Re functionalities can

be controlled and all the ICs can be seen as a register map made by 128 register of 16-bit

each.

The SPI is a simple industry standard communications interface commonly used in

embedded systems and it has the following four I/O pins:

–

Miso (master input slave output)

–

Mosi (Master Output Slave Input)

–

sclk (serial clock [controlled by the master])

–

nSS (slave select active low [controlled by the master])

The “Miso” (master in, slave out) signal carries synchronous data from the slave to the

master device. The mosi (master out, slave in) signal carries synchronous data from the

master to the slave device. The sclk signal is driven by the master, synchronizing all data

transfers. Each SPI slave device has one nSS signal that is an active-low slave input/master

output pin. Slave devices do not respond to transactions unless their nSS input signal is

driven low. Master device interfacing with multiple SPI slave devices has an nSS signal for

each slave device.

S.A.B.Re will maintain its miso pin in high impedance until it does not recognize its address

in serial frame.

23.1

Read transaction

A read transaction (see Figure 43) is always started by the master device that lowers the

nSS pin. The other bits are then sent on the mosi pin with this order:

7-bit representing the address of the register that must be read (MSB first [A6…A0]);

2-bit that must be “10” for a read transaction;

2-bit representing S.A.B.Re IC address;

1-bit reserved for future use that must be set at “0”.

At this point the data stored in the register at the selected address will be shifted out on the

miso pin.

The read operation is terminated by raising the signal on nSS pin.

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