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R8C2K Datasheet(PDF) 189 Page - Renesas Technology Corp

Part # R8C2K
Description  RENESAS MCU R8C FAMILY / R8C/2x SERIES
PDF  471 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R8C2K Datasheet(HTML) 189 Page - Renesas Technology Corp

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R8C/2K Group, R8C/2L Group
16. Timers
Rev.1.10
Dec 21, 2007
Page 172 of 450
REJ09B0406-0110
• Workaround example (b):
As shown in Figure 16.26 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicates the TRBO pin output value.
Figure 16.26
Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
16.2.5.3
Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
(i)
The TRBO output inversion
is detected at the end of the
secondary period.
Ensure sufficient time
Upon detecting (i), set the secondary and
then the primary register immediately.
(ii) (iii)



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