R8C2K datasheet(282/471 Pages) RENESAS

282 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 265 of 450

REJ09B0406-0110

Figure 16.105 Registers TRDSR0 to TRDSR1 in PWM Mode

Timer RD Status Register i (i=0 or 1)

Symbol

Address

After Reset

TRDSR0

TRDSR1

0143h

0153h

11100000b

11000000b

Bit Symbol

Bit Name

Function

NOTES:

—

(b7-b6)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 1.

OVF

UDF

Underflow flag(1)

This bit is disabled in PWM mode.

Input capture/compare match

flag C

[Source for setting this bit to 0]

Write 0 after read(2).

[Source for setting this bit to 1]

When the value in the TRDi register matches w ith

the value in the TRDGRCi register(3).

Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.

IMFC

Input capture/compare match

flag D

[Source for setting this bit to 0]

Write 0 after read(2).

[Source for setting this bit to 1]

When the value in the TRDi register matches w ith

the value in the TRDGRDi register(3).

Overflow flag

[Source for setting this bit to 0]

Write 0 after read(2).

[Source for setting this bit to 1]

When the TRDi register overflow s.

IMFB

Input capture/compare match

flag A

[Source for setting this bit to 0]

Write 0 after read(2).

[Source for setting this bit to 1]

When the value in the TRDi register matches w ith

the value in the TRDGRAi register.

Input capture/compare match

flag B

[Source for setting this bit to 0]

Write 0 after read(2).

[Source for setting this bit to 1]

When the value in the TRDi register matches w ith

the value in the TRDGRBi register.

IMFA

b7 b6 b5 b4

Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).

The w riting results are as follow s:

• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.

• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains

1 even if it is set to 1 from 0 after reading, and w riting 0.)

• This bit remains unchanged if 1 is w ritten.

b3 b2

IMFD

b1 b0

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