R8C2K datasheet(299/471 Pages) RENESAS

299 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 282 of 450

REJ09B0406-0110

i = 0 or 1, j = either A, B, C, or D

NOTE:

1. After a count starts, the PWM period is fixed.

Table 16.45

Complementary PWM Mode Specifications

Item

Specification

Count sources

f1, f2, f4, f8, f32, fOCO40M

External signal input to the TRDCLK pin (valid edge selected by a program)

Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count

source) as bits TCK2 to TCK0 in the TRDCR0 register.

Count operations

Increment or decrement

Registers TRD0 and TRD1 are decremented with the compare match in registers

TRD0 and TRDGRA0 during increment operation. The TRD1 register value is

changed from 0000h to FFFFh during decrement operation, and registers TRD0 and

TRD1 are incremented.

PWM operations

PWM period: 1/fk × (m+2-p) × 2(1)

Dead time: p

Active level width of normal-phase: 1/fk × (m-n-p+1) × 2

Active level width of counter-phase: 1/fk × (n+1-p) × 2

fk: Frequency of count source

m: Value set in the TRDGRA0 register

n: Value set in the TRDGRB0 register (PWM1 output)

Value set in the TRDGRA1 register (PWM2 output)

Value set in the TRDGRB1 register (PWM3 output)

p: Value set in the TRD0 register

Count start condition

1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register.

Count stop conditions

0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register

when the CSEL0 bit in the TRDSTR register is set to 1.

(The PWM output pin holds output level before the count stops.)

Interrupt request generation

timing

• Compare match (The content of the TRDi register matches content of the TRDGRji

• The TRD1 register underflows

TRDIOA0 pin function

Programmable I/O port or TRDCLK (external clock) input

TRDIOB0 pin function

PWM1 output normal-phase output

TRDIOD0 pin function

PWM1 output counter-phase output

TRDIOA1 pin function

PWM2 output normal-phase output

TRDIOC1 pin function

PWM2 output counter-phase output

TRDIOB1 pin function

PWM3 output normal-phase output

TRDIOD1 pin function

PWM3 output counter-phase output

TRDIOC0 pin function

Output inverted every 1/2 period of PWM

INT0 pin function

Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input

Read from timer

The count value can be read by reading the TRDi register.

Write to timer

The value can be written to the TRDi register.

Select functions

• Pulse output forced cutoff signal input (Refer to 16.4.4 Pulse Output Forced

Cutoff.

)

• The active level of normal-phase and counter-phase and initial output level

selected individually

• Transfer timing from the buffer register selected

• A/D trigger generated

n+1

Normal-phase

(When “L” is selected as the active level)

Counter-phase

m+2-p

n+1-p

m-p-n+1

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