R5F72115D160FPV datasheet(354/1228 Pages) RENESAS

Part #	R5F72115D160FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family

PDF	1228 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 330 of 1200

REJ09B0344-0200

Table 9.6

Selecting External Request Detection with DL and DS Bits

CHCR

DL bit

DS bit

Detection of External Request

Low level detection

Falling edge detection

High level detection

Rising edge detection

When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive

period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again

enters the request accept enabled state.

When DREQ is used by level detection, there are following two cases by the timing to detect the

next DREQ after outputting DACK.

Overrun 0: Transfer is terminated after the same number of transfer has been performed as

requests.

Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests

plus 1) times.

The DO bit in CHCR selects this overrun 0 or overrun 1.

Table 9.7

Selecting External Request Detection with DO Bit

CHCR

DO bit

External Request

Overrun 0

Overrun 1

R5F72115D160FPV Datasheet(PDF) 354 Page - Renesas Technology Corp