R5F72115D160FPV datasheet(363/1228 Pages) RENESAS

363 / 1228 page

Section 9 Direct Memory Access Controller (DMAC)

Rev. 2.00 May. 08, 2008 Page 339 of 1200

REJ09B0344-0200

(b)

Single Address Mode

In single address mode, both the transfer source and destination are external devices, either of

them is accessed (selected) by the DACK signal, and the other device is accessed by an address. In

this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external

devices by outputting the DACK transfer request acknowledge signal to it, and at the same time

outputting an address to the other device involved in the transfer. For example, in the case of

transfer between external memory and an external device with DACK shown in figure 9.7, when

the external device outputs data to the data bus, that data is written to the external memory in the

same bus cycle.

External address bus

External data bus

DMAC

External

memory

DACK

DREQ

Data flow (from memory to device)

Data flow (from device to memory)

External device

with DACK

This LSI

Figure 9.7 Data Flow in Single Address Mode

Two kinds of transfer are possible in single address mode: (1) transfer between an external device

with DACK and a memory-mapped external device, and (2) transfer between an external device

with DACK and external memory. In both cases, only the external request signal (DREQ) is used

for transfer requests.

Figure 9.8 shows an example of DMA transfer timing in single address mode.

R5F72115D160FPV Datasheet(PDF) 363 Page - Renesas Technology Corp