R5F72115D160FPV datasheet(773/1228 Pages) RENESAS

773 / 1228 page

Section 16 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 May. 08, 2008 Page 749 of 1200

REJ09B0344-0200

16.4.4

Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs

the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,

refer to figures 16.9 and 16.10.

The transmission procedure and operations in slave transmit mode are described below.

1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and

TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches.

2. When the slave address matches in the first frame following detection of the start condition,

the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th

clock pulse. At this time, if the 8th bit data (R/

W) is 1, the TRS bit in ICCR1 and the TDRE bit

in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The

continuous transmission is performed by writing transmit data to ICDRT every time TDRE is

set.

3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,

with TDRE = 1. When TEND is set, clear TEND.

4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is opened.

5. Clear TDRE.

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