R5F72115D160FPV datasheet(1011/1228 Pages) RENESAS

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Section 22 On-Chip RAM

Rev. 2.00 May. 08, 2008 Page 987 of 1200

REJ09B0344-0200

Section 22 On-Chip RAM

This LSI has an on-chip RAM module which can be used to store instructions or data.

On-chip RAM operation and write access to the RAM can be enabled or disabled through the

RAM enable bits and RAM write enable bits.

22.1

Features

• Pages

The on-chip RAM is divided into four pages (pages 0 to 3).

• Memory map

The on-chip RAM is located in the address spaces shown in table 22.1.

Table 22.1

On-Chip RAM Address Spaces

Page

Address

Page 0

H'FFF80000 to H'FFF81FFF

Page 1

H'FFF82000 to H'FFF83FFF

Page 2

H'FFF84000 to H'FFF85FFF

Page 3

H'FFF86000 to H'FFF87FFF

• Ports

Each page has two independent read and write ports and is connected to the internal bus (I

bus), CPU instruction fetch bus (F bus), and CPU memory access bus (M bus). (Note that the F

bus is connected only to the read ports.)

The F bus and M bus are used for access by the CPU, and the I bus is used for access by the

DMAC.

• Priority

When the same page is accessed from different buses simultaneously, the access is processed

according to the priority. The priority is I bus

> M bus > F bus.

R5F72115D160FPV Datasheet(PDF) 1011 Page - Renesas Technology Corp