R5F72115D160FPV datasheet(215/1228 Pages) RENESAS

215 / 1228 page

Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 191 of 1200

REJ09B0344-0200

8.4.3

CSn Space Wait Control Register (CSnWCR) (n = 0 to 7)

CSnWCR specifies various wait cycles for memory access. The bit configuration of this register

varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn

space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify

CSnBCR first, then specify CSnWCR.

CSnWCR is initialized to H'00000500 by a power-on reset and retains the value by a manual reset

and in software standby mode.

(1)

Normal Space, SRAM with Byte Selection, MPX-I/O

• CS0WCR

0000000000000000

R/W

0000010100000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

-----------

BAS

----

SW[1:0]

WR[3:0]

HW[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21

⎯ *

All 0

R/W

Reserved

These bits are always read as 0. The write value

should always be 0.

BAS*

R/W

Byte Access Selection when SRAM with Byte

Selection is Used

Specifies the

WEn and RD/WR signal timing when the

SRAM interface with byte selection is used.

0: Asserts the

WEn signal at the read/write timing and

asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn signal during the read/write access

cycle and asserts the RD/

WR signal at the write

timing.

R5F72115D160FPV Datasheet(PDF) 215 Page - Renesas Technology Corp

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