R5F72115D160FPV datasheet(318/1228 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 2.00 May. 08, 2008 Page 294 of 1200

REJ09B0344-0200

The sequence for reclaiming the bus mastership from an external device is described below. 1.5

cycles after the negation of

BREQ is detected at the falling edge of CK, the bus control signals are

driven high. The bus acknowledge signal is negated at the next falling edge of the clock. The

fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the

rising edge of the CK where address and data signals are driven. Figure 8.40 shows the bus

arbitration timing.

When it is necessary to refresh SDRAM while releasing the bus mastership, the bus mastership

should be returned using the

REFOUT signal. For details on the selection of REFOUT, see section

19, Pin Function Controller (PFC). The

REFOUT signal is kept asserting at low level until the bus

mastership is acquired. The

BREQ signal is negated by asserting the REFOUT signal and the bus

mastership is returned from the external device. If the bus mastership is not returned for a

refreshing period or longer, the contents of SDRAM cannot be guaranteed because a refreshing

cannot be executed.

While releasing the bus mastership, the SLEEP instruction (to enter sleep mode or standby mode),

as well as a manual reset, cannot be executed until the LSI obtains the bus mastership.

The

BREQ input signal is ignored in standby mode and the BACK output signal is placed in the

high impedance state. If the bus mastership request is required in this state, the bus mastership

must be released by pulling down the

BACK pin to enter standby mode.

The bus mastership release (

BREQ signal for high level negation) after the bus mastership request

(

BREQ signal for low level assertion) must be performed after the bus usage permission (BACK

signal for low level assertion). If the

BREQ signal is negated before the BACK signal is asserted,

only one cycle of the

BACK signal is asserted depending on the timing of the BREQ signal to be

negated and this may cause a bus contention between the external device and the LSI.

Other bus

contorol sigals

BREQ

BACK

A25 to A0

D15 to D0

CSn

Figure 8.40 Bus Arbitration Timing (Clock Mode 7 or CMNCR.HIZCNT = 1)

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