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M16C/29 Datasheet(PDF) 299 Page - Renesas Technology Corp |
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M16C/29 Datasheet(HTML) 299 Page - Renesas Technology Corp |
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299 / 499 page  16. MULTI-MASTER I2C bus INTERFACE p u o r G 9 2 / C 6 1 M page 275 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R 16.7 I2C0 Control Register 2 (S4D0 Register) The S4D0 register controls the error communication detection. If the SCL clock is stopped counting dring data transfer, each device is stopped, staying online. To avoid the situation, the I2C bus interface circuit has a function to detect the time-out when the SCL clock is stopped in high-level ("H") state for a specific period, and to generate an I2C bus interface interrupt request. See Figure 16.13. Figure 16.13 The timing of time-out detection 1 clock 1 bit SCL SDA BB flag Internal counter start signal Internal counter stop, reset signal Internal counter overflow signal I2C-bus interface interrupt request signal 2 bit 3 bit 2 clock 3 clock SCL clock stop (“H”) The time of timeout detection |
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