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H838532H Datasheet(PDF) 373 Page - Renesas Technology Corp |
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H838532H Datasheet(HTML) 373 Page - Renesas Technology Corp |
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373 / 508 page ![]() Section 12 A/D Converter Rev. 1.00 May 30, 2008 Page 353 of 484 REJ09B0436-0100 Bit 7: Clock select (CKS) Bit 7 sets the A/D conversion speed. Bit 7 Conversion Time (Active (High-Speed) Mode)* CKS Conversion Period φ = 1 MHz φ = 5 MHz 0 62/ φ (initial value) 62 µs 12.4 µs 1 31/ φ 31 µs — Note: * For information on conversion time settings for which operation is guaranteed, see section 16, Electrical Characteristics. Bit 6: External trigger select (TRGE) Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6 TRGE Description 0 Disables start of A/D conversion by external trigger (initial value) 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* Note: * The external trigger ( ADTRG) edge is selected by bit IEG4 of IEGR. See (1) IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control Registers, for details. Bits 5 and 4: Reserved bits Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. |
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