H838532H datasheet(382/508 Pages) RENESAS

382 / 508 page

Section 12 A/D Converter

Rev. 1.00 May 30, 2008 Page 362 of 484

REJ09B0436-0100

12.6

Application Notes

12.6.1

Application Notes

• Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D

start register (ADSR) is cleared to 0.

• Changing the digital input signal at an adjacent pin during A/D conversion may adversely

affect conversion accuracy.

• When A/D conversion is started after clearing module standby mode, wait for 10 φ clock

cycles before starting.

• In active mode or sleep mode, analog power supply current (AI

STOP1) flows into the ladder

resistance even when the A/D converter is not operating. Therefore, if the A/D converter is not

used, it is recommended that AV

CC be connected to the system power supply and the

ADCKSTP(A/D converter module standby mode control) bit be cleared to 0 in clock stop

12.6.2

Permissible Signal Source Impedance

This LSI’s analog input is designed such that conversion precision is guaranteed for an input

signal for which the signal source impedance is 10 k

Ω or less. This specification is provided to

enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the

sampling time; if the sensor output impedance exceeds 10 k

Ω, charging may be insufficient and it

may not be possible to guarantee A/D conversion precision. However, a large capacitance

provided externally, the input load will essentially comprise only the internal input resistance of

10 k

Ω, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained

in this case, it may not be possible to follow an analog signal with a large differential coefficient

(e.g., 5 mV/

µs or greater) (see figure 12.6). When converting a high-speed analog signal, a low-

impedance buffer should be inserted.

H838532H Datasheet(PDF) 382 Page - Renesas Technology Corp