H838532H datasheet(391/508 Pages) RENESAS

391 / 508 page

Section 13 LCD Controller/Driver

Rev. 1.00 May 30, 2008 Page 371 of 484

REJ09B0436-0100

Bit 4: Display data control (DISP)

Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless

of the LCD RAM contents.

Bit 4

DISP

Description

Blank data is displayed

(initial value)

LCD RAM data is display

Bits 3 to 0: Frame frequency select 3 to 0 (CKS3 to CKS0)

Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,

and subsleep mode, the system clock (

φ) is halted, and therefore display operations are not

performed if one of the clocks from

φ/2 to φ/256 is selected. If LCD display is required in these

modes,

φw, φw/2, or φw/4 must be selected as the operating clock.

Frame Frequency*

Bit 3

CKS3

Bit 2

CKS2

Bit 1

CKS1

Bit 0

CKS0

Operating Clock

φ = 2 MHz

φ = 250 kHz*1

φw

128 Hz*

3 (initial value)

φw/2

64 Hz*

φw/4

32 Hz*

φ/2

—

244 Hz

φ/4

977 Hz

122 Hz

φ/8

488 Hz

61 Hz

φ/16

244 Hz

30.5 Hz

φ/32

122 Hz

—

φ/64

61 Hz

—

φ/128

30.5 Hz

—

φ/256

—

*: Don’t care

Notes: 1. This is the frame frequency in active (medium-speed,

φosc/16) mode when φ = 2 MHz.

2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.

3. This is the frame frequency when

φw = 32.768 kHz.

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