H8S2245 datasheet(489/818 Pages) RENESAS

489 / 818 page

Section 12 Serial Communication Interface (SCI)

Rev.3.00 Mar. 26, 2007 Page 447 of 772

REJ09B0355-0300

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR

[2]

Write transmit data to TDR and

set MPBT bit in SSR

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and set DDR to 1

Clear TE bit in SCR to 0

TDRE = 1?

All data transmitted?

TEND = 1?

Break output?

Clear TDRE flag to 0

SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1, a

frame of 1s is output, and

transmission is enabled.

SCI status check and transmit

data write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR. Set the

MPBT bit in SSR to 0 or 1.

Finally, clear the TDRE flag to 0.

Serial transmission continuation

procedure:

To continue serial transmission,

be sure to read 1 from the TDRE

flag to confirm that writing is

possible, then write data to TDR,

and then clear the TDRE flag to

0. Checking and clearing of the

TDRE flag is automatic when the

DTC* is activated by a transmit

data empty interrupt (TXI)

request, and data is written to

TDR.

Break output at the end of serial

transmission:

To output a break in serial

transmission, set the port DDR to

1, clear DR to 0, then clear the

TE bit in SCR to 0.

[1]

[2]

[3]

[4]

Note: * The case, in which the DTC

automatically clears the TDRE

flag, occurs only when DISEL in

DTC is 0 with the transfer

counter not being 0. Therefore,

the TDRE flag should be cleared

by CPU when DISEL is 1, or

when DISEL is 0 with the

transfer counter being 0.

Figure 12.10 Sample Multiprocessor Serial Transmission Flowchart

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