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H8S2245 Datasheet(PDF) 508 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 508 Page - Renesas Technology Corp |
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508 / 818 page ![]() Section 12 Serial Communication Interface (SCI) Rev.3.00 Mar. 26, 2007 Page 466 of 772 REJ09B0355-0300 Internal basic clock 16 clocks 8 clocks Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing 15 0 7 15 0 07 Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. M = | (0.5 – 1 2N ) – (L – 0.5) F – | D – 0.5 | N (1 + F) | × 100% ... Formula (1) Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 – 1 2 × 16 ) × 100% = 46.875% ... Formula (2) However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. |
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