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H8S2245 Datasheet(PDF) 519 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 519 Page - Renesas Technology Corp |
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519 / 818 page  Section 13 Smart Card Interface Rev.3.00 Mar. 26, 2007 Page 477 of 772 REJ09B0355-0300 13.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 13.2.1 Smart Card Mode Register (SCMR) Bit : 76 543210 —— —— SDIR SINV — SMIF Initial value : 11 110010 R/W : —— —— R/W R/W — R/W SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4—Reserved: Read-only bits, always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR Description 0 TDR contents are transmitted LSB-first (Initial value) Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 13.3.4, Register Settings. |
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