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H8S2245 Datasheet(PDF) 542 Page - Renesas Technology Corp

Part # H8S2245
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S2245 Datasheet(HTML) 542 Page - Renesas Technology Corp

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Section 13 Smart Card Interface
Rev.3.00 Mar. 26, 2007 Page 500 of 772
REJ09B0355-0300
Retransfer Operations
Retransfer operations are performed by the SCI in receive mode and transmit mode as described
below.
• Retransfer operation when SCI is in receive mode
Figure 13.11 illustrates the retransfer operation when the SCI is in receive mode.
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to
have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE
bit in SCR is enabled at this time, an RXI interrupt request is generated.
If DTC data transfer by an RXI source is enabled, the contents of RDR can be read
automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared
to 0 if DISEL in DTC is 0 and the transfer counter value is not 0.
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for
error signal transmission.
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
Ds
Transfer
frame n+1
Retransferred frame
nth transfer frame
RDRF
[1]
PER
[2]
[3]
[4]
Figure 13.11 Retransfer Operation in SCI Receive Mode



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