H8S2245 datasheet(687/818 Pages) RENESAS

687 / 818 page

Appendix B Register Field

Rev.3.00 Mar. 26, 2007 Page 645 of 772

REJ09B0355-0300

MRB—DTC Mode Register B

H'F800—H'FBFF

DTC

CHNE

Undefined

—

DISEL

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

DTC Chain Transfer Enable

End of DTC data transfer

DTC chain transfer

DTC Interrupt Select

After a data transfer ends, the CPU interrupt is

disabled unless the transfer counter is 0

After a data transfer ends, the CPU interrupt is enabled

SAR—DTC Source Address Register

H'F800—H'FBFF

DTC

Bit

Initial value

Read/Write

43210

- - -

Specifies transfer data source address

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

——

—

DAR—DTC Destination Address Register

H'F800—H'FBFF

DTC

Bit

Initial value

Read/Write

43210

- - -

Specifies transfer data destination address

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

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