H8S2245 datasheet(731/818 Pages) RENESAS

731 / 818 page

Appendix B Register Field

Rev.3.00 Mar. 26, 2007 Page 689 of 772

REJ09B0355-0300

SSR1—Serial Status Register 1

H'FF84

SCI1

TDRE

R/(W)*1

RDRF

R/(W)*1

ORER

R/(W)*1

FER

R/(W)*1

PER

R/(W)*1

MPBT

R/W

TEND

MPB

Notes: 1. Can only be written with 0 for flag clearing.

2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.

Transmit Data Register Empty

Receive Data Register Full

Overrun Error

Framing Error

Parity Error

Transmit End

Multiprocessor Bit

[Clearing condition]

When data with a 0 multiprocessor bit is received

Multiprocessor Bit Transfer

Data with a 0 multiprocessor bit is transmitted

Data with a 1 multiprocessor bit is transmitted

Bit

Initial value

Read/Write

[Setting condition]

When data with a 1 multiprocessor bit is received

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC*2 is activated by a TXI interrupt and write data to TDR

[Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of a 1-byte

serial transmit character

[Clearing condition]

When 0 is written to PER after reading PER = 1

[Setting condition]

When, in reception, the number of 1 bits in the receive data plus the parity bit

does not match the parity setting (even or odd) specified by the O/

E bit in SMR

[Clearing condition]

When 0 is written to FER after reading FER = 1

[Setting condition]

When the SCI checks whether the stop bit at the end of the receive

data is 1 when reception ends, and the stop bit is 0

[Clearing condition]

When 0 is written to ORER after reading ORER = 1

[Setting condition]

When the next serial reception is completed while RDRF = 1

[Clearing conditions]

• When 0 is written to RDRF after reading RDRF = 1

• When the DTC*2 is activated by an RXI interrupt and read data from RDR

[Setting condition]

When serial reception ends normally and receive data is transferred

from RSR to RDR

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC*2 is activated by a TXI interrupt and write data to TDR

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written to TDR

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