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H8S2245 Datasheet(PDF) 756 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 756 Page - Renesas Technology Corp |
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756 / 818 page  Appendix B Register Field Rev.3.00 Mar. 26, 2007 Page 714 of 772 REJ09B0355-0300 TIOR0L—Timer I/O Control Register 0L H'FFD3 TPU0 0 1 TGR0D I/O Control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 TGR0C I/O Control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * Legend: *: Don't care Legend: *: Don't care Note: 1. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 0 IOC0 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Bit Initial value Read/Write : : : : TGR0C is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Initial output is 0 output TGR0C is input capture register*1 Output disabled Initial output is 1 output Capture input source is TIOCC0 pin Setting prohibited TGR0D is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Initial output is 0 output TGR0D is input capture register*1 Output disabled Initial output is 1 output Capture input source is TIOCD0 pin Setting prohibited |
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