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H8S2245 Datasheet(PDF) 766 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 766 Page - Renesas Technology Corp |
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766 / 818 page ![]() Appendix B Register Field Rev.3.00 Mar. 26, 2007 Page 724 of 772 REJ09B0355-0300 TCR2—Timer Control Register 2 H'FFF0 TPU2 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture Counter Clear 0 1 0 1 0 1 0 1 Clock Edge 0 1 — Count at rising edge Count at falling edge Count at both edges Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024 Time Prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 — 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 0 TPSC0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W Note: This setting is ignored when channel 2 is in phase counting mode. Bit Initial value Read/Write : : : Note: This setting is ignored when channel 2 is in phase counting mode. TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation |
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