H8S2245 datasheet(279/818 Pages) RENESAS

279 / 818 page

Section 8 I/O Ports

Rev.3.00 Mar. 26, 2007 Page 237 of 772

REJ09B0355-0300

Port 5 Data Direction Register (P5DDR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

P53DDR

P50DDR

P52DDR

P51DDR

Bit

Initial value

R/W

P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 5. Bits 7 to 4 are reserved. P5DDR cannot be read; if it is, an undefined value will be

read. P5DDR cannot be modified.

Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit

to 0 makes the pin an input pin.

This register is a write-only register, and cannot be written by bit manipulation instruction. For

details, see section 2.10.4, Access Methods for Registers with Write-Only Bits.

P5DDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It

retains its prior state after a manual reset, and in software standby mode. As the SCI is initialized

by a reset and in standby mode, the pin states are determined by the P5DDR and P5DR

specifications.

Port 5 Data Register (P5DR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

P53DR

R/W

P50DR

R/W

P52DR

R/W

P51DR

R/W

Bit

Initial value

R/W

P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P5

3 to P50).

Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.

P5DR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It

retains its prior state after a manual reset, and in software standby mode.

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