H8S2245 datasheet(285/818 Pages) RENESAS

285 / 818 page

Section 8 I/O Ports

Rev.3.00 Mar. 26, 2007 Page 243 of 772

REJ09B0355-0300

Port A MOS Pull-Up Control Register (PAPCR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

PA3PCR

R/W

PA0PCR

R/W

PA2PCR

R/W

PA1PCR

R/W

Bit

Initial value

R/W

PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port A on an individual bit basis.

Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.

Bits 3 to 0 are valid in modes 1, 2, 3, 6, and 7, and all the bits are invalid in modes 4 and 5. When

a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on

the MOS input pull-up for the corresponding pin.

PAPCR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It

retains its prior state after a manual reset, and in software standby mode.

Port A Open Drain Control Register (PAODR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

PA3ODR

R/W

PA0ODR

R/W

PA2ODR

R/W

PA1ODR

R/W

Bit

Initial value

R/W

PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each

port A pin (PA

3 to PA0).

Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.

All bits are valid in modes 1, 2, 3, and 7.

Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while

clearing the bit to 0 makes the pin a CMOS output.

PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It

retains its prior state after a manual reset, and in software standby mode.

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