HD6432351 datasheet(435/1025 Pages) RENESAS

435 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 401 of 988

REJ09B0330-0300

Pins PF2 to PF0 are designated as bus control input/output pins (LCAS, WAIT, BREQO,

BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1

makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an

input port.

• Modes 3 and 7 [H8S/2351 only]

Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in

the case of pin PF7, the φ output pin. Clearing the bit to 0 makes the pin an input port.

Port F Data Register (PFDR)

PF7DR

R/W

PF6DR

R/W

PF5DR

R/W

PF4DR

R/W

PF3DR

R/W

PF0DR

R/W

PF2DR

R/W

PF1DR

R/W

Bit

Initial value

R/W

PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).

PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior

state after a manual reset, and in software standby mode.

Port F Register (PORTF)

PF7

—*

PF6

—*

PF5

—*

PF4

—*

PF3

—*

PF0

—*

PF2

—*

PF1

—*

Bit

Initial value

R/W

Note: * Determined by state of pins PF7 to PF0.

PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port

F pins (PF7 to PF0) must always be performed on PFDR.

If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F

read is performed while PFDDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin

states, as PFDDR and PFDR are initialized. PORTF retains its prior state after a manual reset, and

in software standby mode.

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