HD6432351 datasheet(475/1025 Pages) RENESAS

475 / 1025 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 441 of 988

REJ09B0330-0300

Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D

conversion start requests by TGRA input capture/compare match.

Bit 7

TTGE

Description

A/D conversion start request generation disabled

(Initial value)

A/D conversion start request generation enabled

Bit 6—Reserved: Read-only bit, always read as 1.

Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by

the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2.

In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.

Bit 5

TCIEU

Description

Interrupt requests (TCIU) by TCFU disabled

(Initial value)

Interrupt requests (TCIU) by TCFU enabled

Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by

the TCFV flag when the TCFV flag in TSR is set to 1.

Bit 4

TCIEV

Description

Interrupt requests (TCIV) by TCFV disabled

(Initial value)

Interrupt requests (TCIV) by TCFV enabled

Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the

TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.

Bit 3

TGIED

Description

Interrupt requests (TGID) by TGFD bit disabled

(Initial value)

Interrupt requests (TGID) by TGFD bit enabled

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