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HD6432351 Datasheet(PDF) 503 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 503 Page - Renesas Technology Corp |
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503 / 1025 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Sep 15, 2006 page 469 of 988 REJ09B0330-0300 Examples of Cascaded Operation Figure 10.22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A. TCNT2 clock TCNT2 H'FFFF H'0000 H'0001 TIOCA1, TIOCA2 TGR1A H'03A2 TGR2A H'0000 TCNT1 clock TCNT1 H'03A1 H'03A2 Figure 10.22 Example of Cascaded Operation (1) Figure 10.23 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, and phase counting mode has been designated for channel 2. TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow. |
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