HD6432351 datasheet(549/1025 Pages) RENESAS

549 / 1025 page

Section 11 Programmable Pulse Generator (PPG)

Rev. 3.00 Sep 15, 2006 page 515 of 988

REJ09B0330-0300

Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits

select the compare match that triggers pulse output group 1 (pins PO7 to PO4).

Description

Bit 3

G1CMS1

Bit 2

G1CMS0

Output Trigger for Pulse Output Group 1

Compare match in TPU channel 0

Compare match in TPU channel 1

Compare match in TPU channel 2

Compare match in TPU channel 3

(Initial value)

Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits

select the compare match that triggers pulse output group 0 (pins PO3 to PO0).

Description

Bit 1

G0CMS1

Bit 0

G0CMS0

Output Trigger for Pulse Output Group 0

Compare match in TPU channel 0

Compare match in TPU channel 1

Compare match in TPU channel 2

Compare match in TPU channel 3

(Initial value)

11.2.6

PPG Output Mode Register (PMR)

G3INV

R/W

G2INV

R/W

G1INV

R/W

G0INV

R/W

G3NOV

R/W

G0NOV

R/W

G2NOV

R/W

G1NOV

R/W

Bit

Initial value

R/W

PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping

operation for each group.

The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB

and the non-overlap margin is set in TGRA. The output values change at compare match A and B.

For details, see section 11.3.4, Non-Overlapping Pulse Output.

PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

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