HD6432351 datasheet(591/1025 Pages) RENESAS

591 / 1025 page

Section 13 Serial Communication Interface (SCI)

Rev. 3.00 Sep 15, 2006 page 557 of 988

REJ09B0330-0300

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1.

The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.

Bit 3

MPIE

Description

Multiprocessor interrupts disabled (normal reception performed)

(Initial value)

[Clearing conditions]

• When the MPIE bit is cleared to 0

• When MPB= 1 data is received

Multiprocessor interrupts enabled*

Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting

of the RDRF, FER, and ORER flags in SSR are disabled until data with the

multiprocessor bit set to 1 is received.

Note:

* When receive data including MPB = 0 is received, receive data transfer from RSR to

RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR,

is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR

is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI

interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag

setting is enabled.

Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt

(TEI) request generation when there is no valid transmit data in TDR in MSB data transmission.

Bit 2

TEIE

Description

Transmit end interrupt (TEI) request disabled*

(Initial value)

Transmit end interrupt (TEI) request enabled*

Note:

* TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then

clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.

HD6432351 Datasheet(PDF) 591 Page - Renesas Technology Corp