Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

HD6432351 Datasheet(PDF) 614 Page - Renesas Technology Corp

Part # HD6432351
Description  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 Datasheet(HTML) 614 Page - Renesas Technology Corp

Back Button HD6432351 Datasheet HTML 610Page - Renesas Technology Corp HD6432351 Datasheet HTML 611Page - Renesas Technology Corp HD6432351 Datasheet HTML 612Page - Renesas Technology Corp HD6432351 Datasheet HTML 613Page - Renesas Technology Corp HD6432351 Datasheet HTML 614Page - Renesas Technology Corp HD6432351 Datasheet HTML 615Page - Renesas Technology Corp HD6432351 Datasheet HTML 616Page - Renesas Technology Corp HD6432351 Datasheet HTML 617Page - Renesas Technology Corp HD6432351 Datasheet HTML 618Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 614 / 1025 page
background image
Section 13 Serial Communication Interface (SCI)
Rev. 3.00 Sep 15, 2006 page 580 of 988
REJ09B0330-0300
Serial data transmission (asynchronous mode): Figure 13.5 shows a sample flowchart for serial
transmission.
The following procedure should be used for serial data transmission.
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR
[2]
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC or DTC
is activated by a transmit data
empty interrupt (TXI) request, and
data is written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Figure 13.5 Sample Serial Transmission Flowchart



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com