HD6432351 datasheet(667/1025 Pages) RENESAS

667 / 1025 page

Section 14 Smart Card Interface

Rev. 3.00 Sep 15, 2006 page 633 of 988

REJ09B0330-0300

With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible.

If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests

are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in

reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI)

request will be generated.

If the DMAC or DTC is activated by an RXI request, the receive data in which the error occurred

is skipped, and only the number of bytes of receive data set in the DMAC or DTC are transferred.

For details, see Interrupt Operation and Data Transfer Operation by DMAC or DTC below.

If a parity error occurs during reception and the PER is set to 1, the received data is still

transferred to RDR, and therefore this data can be read.

Mode Switching Operation

When switching from receive mode to transmit mode, first confirm that the receive operation has

been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The

RDRF flag or the PER and ORER flags can be used to check that the receive operation has been

completed.

When switching from transmit mode to receive mode, first confirm that the transmit operation has

been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The

TEND flag can be used to check that the transmit operation has been completed.

Fixing Clock Output Level

When the GSM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and

CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.

Figure 14.8 shows the timing for fixing the clock output level. In this example, GSM is set to 1,

CKE1 is cleared to 0, and the CKE0 bit is controlled.

HD6432351 Datasheet(PDF) 667 Page - Renesas Technology Corp